Manufacturing method of semiconductor device

ABSTRACT

A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of an application Ser. No. 11/557,112,filed on Nov. 7, 2006, now pending, which claims the priority benefit ofU.S. provisional applications Ser. No. 60/597,210, filed on Nov. 17,2005 and 60/743,630, filed on Mar. 22, 2006. The entirety of each of theabove-mentioned patent applications are hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a manufacturing method of a semiconductordevice, and more particularly to a manufacturing method of asemiconductor device which raises the limit of high-voltage stress.

2. Description of Related Art

A Metal Oxide Semiconductor (MOS) transistor device is one of the mostimportant and fundamental electronic units among various electronicproducts. Since the invention of MOS transistor devices, people areconstantly aiming for reducing the size of semiconductors; namely, moresemiconductor devices are squeezed in a specific area so as to enhanceand accelerate the performance of computation.

As the level of integration of integrated circuits increases, thedimensions of semiconductor devices decrease correspondingly.Accordingly, as the dimension of a Metal Oxide Semiconductor (MOS)transistor is reduced, the channel length also reduces. However, thedimension of the channel of a MOS transistor cannot be unlimitedlyreduced. As the channel length of a semiconductor device reduces to acertain degree, various problems gradually emerge, which are generallyso-called “short channel effects”. More specifically, when the channellength is decreased and the voltage applied remains unchanged, not onlythe operation speed of the transistor but also the lateral electricfield in the channel is increased. Thereby, the energy of the channelelectrons is increased, especially for the channel electrons near thedrain region. The energy of these electrons is greater than the band gapof the semiconductor. Therefore, after colliding with valence-bandelectrons near the drain region, the channel electrons easily excite thevalence-band electrons thereat to the conductive band and hot electronsare then formed. Parts of the hot electrons enter a gate oxide layer andcause damages, so that the reliability and the lifetime of the deviceare reduced. Especially when the dimension of a MOS transistor device isfurther reduced to a nanometer scale, the short channel effect and thepunch through effect would become more serious, and a further sizereduction of the semiconductor device is then hindered. Therefore, it isa common objective in the industry to produce a semiconductor devicewith small size, high integration, and high quality.

SUMMARY OF THE INVENTION

This invention is to provide a semiconductor device and the method offabricating the same. The semiconductor device has a simple structureand a high breakdown voltage so as to raise the limit of high-voltagestress and to be operated under high voltage.

This invention provides a semiconductor device, including a gate, asecond conductive type drain region, a second conductive type sourceregion, and a second conductive type first lightly doped region. Thegate is formed on a first conductive type substrate. The secondconductive type drain region and the second conductive type sourceregion are formed in the first conductive type substrate at both sidesof the gate. The second conductive type first lightly doped region isformed between the gate and the second conductive type source region.

According to an embodiment of the present invention, the firstconductive type is a P-type while a second conductive type is an N-type.Conversely, the second conductive type is a P-type while the firstconductive type is an N-type.

According to an embodiment of the present invention, the semiconductordevice further includes a first dielectric layer. The first dielectriclayer is formed between the gate and the first conductive typesubstrate, wherein the first dielectric layer has a first thickness at aside of the second conductive type source region and a second thicknessat a side of the second conductive type drain region. The firstthickness is larger than the second.

According to an embodiment of the present invention, the semiconductordevice further includes a first conductive type lightly doped region.The first conductive type lightly doped region is formed between thegate and the second conductive type drain region.

According to an embodiment of the present invention, the semiconductordevice further includes a second conductive type second lightly dopedregion. The second conductive type second lightly doped region is formedbetween the gate and the second conductive type drain region. The secondconductive type first lightly doped region contains a different dopantconcentration from the second conductive type second lightly dopedregion.

According to an embodiment of the present invention, the semiconductordevice further includes insulating spacers. The insulating spacers areformed on the side walls of the gate.

According to an embodiment of the present invention, the material of theinsulating spacers includes silicon nitride or silicon oxide.

Inasmuch as a lightly doped region having a same conductive type as thesource region is formed between the source region and the gate, but nolightly doped region is formed between the drain region and the gate.Even forming a neutral substrate at the sides of the drain region orforming a lightly doped region with an opposite conductive type to thedrain region at the sides of the drain region are two other alternativesfor the semiconductor device of the present invention.

Thus, a high breakdown voltage is then provided to raise the limit ofhigh-voltage stress of the MOS device and to operate the semiconductordevice of the present invention under a high voltage.

The invention provides a method for fabricating a semiconductor device.The fabricating process is described below. First, a first conductivetype substrate is provided, and a gate is formed on the first conductivetype substrate. Then, a second conductive type first lightly dopedregion is formed in the substrate at a first side of the gate.Thereafter, a second conductive type source region is formed in thesubstrate at the first side of the gate, and a second conductive typedrain region is formed at a second side of the gate, wherein the secondconductive type first lightly doped region is formed in the firstconductive type substrate between the second conductive type sourceregion and the gate.

According to an embodiment of the present invention, the firstconductive type is a P-type while a second conductive type is an N-type.Conversely, the first conductive type is an N-type while the secondconductive type is a P-type.

According to an embodiment of the present invention, the method furtherincludes a step of forming a first dielectric layer on the firstconductive type substrate before the step of forming the gate on thefirst conductive type substrate.

According to an embodiment of the present invention, the firstdielectric layer has a first thickness at a first side and a secondthickness at a second side. The second thickness is larger than thefirst.

According to an embodiment of the present invention, the steps offorming the second conductive type first lightly doped region in thefirst conductive type substrate at the first side of the gate areprovided as following. First, a patterned photoresist layer exposing thefirst conductive type substrate at the first side of the gate is formedon the substrate. An ion implantation process is then performed to formthe second conductive type first lightly doped region. Afterward, thepatterned photoresist layer is removed.

According to an embodiment of the present invention, the method furtherincludes a step of forming a first conductive type lightly doped regionin the substrate at the second side of the gate. The first conductivetype lightly doped region is formed between the second conductive typedrain region and the gate.

According to an embodiment of the present invention, the steps offorming the second conductive type first lightly doped region in thefirst conductive type substrate at the first side of the gate, andforming the first conductive type lightly doped region in the substrateat the second side of the gate are provided as following. First, a firstpatterned photoresist layer exposing the first conductive type substrateat the first side of the gate is formed on the substrate. A first ionimplantation process is then performed to form the second conductivetype first lightly doped region. After the first patterned photoresistlayer is removed, a second patterned photoresist layer exposing thefirst conductive type substrate at the second side of the gate is formedon the substrate. A second ion implantation process is then performed toform the first conductive type lightly doped region, and the secondpatterned photoresist layer is removed.

According to an embodiment of the present invention, the method furtherincludes forming a second conductive type second lightly doped region inthe substrate at the second side of the gate. The second conductive typesecond lightly doped region is formed between the second conductive typedrain region and the gate.

According to an embodiment of the present invention, the steps offorming the second conductive type first lightly doped region and thesecond conductive type second lightly doped region in the firstconductive type substrate at the first and the second sides of the gate,and forming the first conductive type lightly doped region in thesubstrate at the second side of the gate are provided as following.First, a first ion implantation process is performed to form the secondconductive type first lightly doped region and the second conductivetype second lightly doped region. A patterned photoresist layer exposingthe first conductive type substrate at the second side of the gate isthen formed on the substrate. After a second ion implantation process isperformed to form the first conductive type lightly doped region, thepatterned photoresist layer is removed.

According to an embodiment of the present invention, the method furtherincludes forming insulating spaces at the side walls of the gate.

The method of fabricating the semiconductor device of the presentinvention has a simple fabricating process which can be integrated withthe fabricating process of a conventional Complementary Metal OxideSemiconductor (CMOS) so as to reduce the time of fabricating the device.Various specific embodiments of the present invention are disclosedbelow, illustrating examples of various possible implementations of theconcepts of the present invention. The following description is made forthe purpose of illustrating the general principles of the invention andshould not be taken in a limiting sense. The scope of the invention isbest determined by reference to the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional view showing a preferredembodiment of the semiconductor device of the present invention.

FIG. 1B is a schematic cross-sectional view showing a preferredembodiment of the semiconductor device of the present invention.

FIG. 1C is a schematic cross-sectional view showing another preferredembodiment of the semiconductor device of the present invention.

FIG. 1D is a schematic cross-sectional view showing yet anotherpreferred embodiment of the semiconductor device of the presentinvention.

FIGS. 2A through 2E are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to a preferredembodiment of the present invention.

FIGS. 3A through 3B are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to a preferredembodiment of the present invention.

FIGS. 4A through 4C are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to anotherpreferred embodiment of the present invention.

FIGS. 5A through 5D are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to a preferredembodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 1A is a schematic cross-sectional view showing a preferredembodiment of the semiconductor device of the present invention.

Please refer to FIG. 1A. The semiconductor device of the presentinvention is, for example, formed on a first conductive type substrate100. The first conductive type substrate 100 is a silicon substrate, forexample. The semiconductor device includes a gate dielectric layer 102,a gate 104, a dielectric layer 106, insulating spacers 108, a secondconductive type source region 110, a second conductive type drain region112, and a second conductive type lightly doped region 114, for example.

The gate 104 is, for example, formed on the first conductive typesubstrate 100. The material of the gate 104 is, for example, dopedpolysilicon.

The gate dielectric layer 102 is, for example, formed between the gate104 and the first conductive type substrate 100. The material of thegate dielectric layer 102 is, for example, silicon oxide.

The second conductive type source region 110 and the second conductivetype drain region 112 are formed in the first conductive type substrate100 at both sides of the gate 104, for example.

The insulating spacers 108 are, for example, formed on the side walls ofthe gate 104. The material of the insulating spacers 108 is siliconoxide or silicon nitride, for example.

The second conductive type lightly doped region 114 is, for example,formed in the first conductive type substrate 100 between the gate 104and the second conductive type source region 110. Namely, it ispositioned under the insulating spacers 108.

In the above-mentioned embodiment, if the first conductive type is aP-type and the second conductive type is an N-type, the semiconductordevice is an N-channel semiconductor device. On the other hand, if thefirst conductive type is an N-type and the second conductive type is aP-type, the semiconductor device is then a P-channel semiconductordevice.

According to the semiconductor device of the present invention, inasmuchas the second conductive type lightly doped region is not formed at thesides of the second conductive type drain region 112, the limit ofhigh-voltage stress of the MOS device can be raised, so that thesemiconductor device of the present invention can be operated under ahigh voltage.

FIG. 1B is a schematic cross-sectional view showing another preferredembodiment of the semiconductor device of the present invention. In FIG.1B, the same reference numbers are used to refer to the same parts inFIG. 1A. Here, only the differences are described.

Please refer to FIG. 1B. The semiconductor device includes a firstconductive type lightly doped region 116 formed at the sides of thesecond conductive type drain region 112. The first conductive typelightly doped region 116 is, for example, formed in the first conductivetype substrate 100 between the gate 104 and the second conductive typedrain region 112. Namely, it is positioned under the insulating spacers108.

According to the semiconductor device shown in FIG. 1B, inasmuch as alightly doped region with an opposite conductive type to thesource/drain region is formed at the sides of the drain region, therebythe limit of high-voltage stress of the MOS device can be raised, sothat the semiconductor device of the present invention can be operatedunder a high voltage.

FIG. 1C is a schematic cross-sectional view showing yet anotherpreferred embodiment of the semiconductor device of the presentinvention. In FIG. 1C, the same reference numbers are used to refer tothe same parts in FIG. 1A. Here, only the differences are described.

Please refer to FIG. 1C. The semiconductor device includes the firstconductive type lightly doped region 116 and a second conductive typelightly doped region 114 a formed at the sides of the second conductivetype drain region 112. The first conductive type lightly doped region116 is, for example, formed in the first conductive type substrate 100between the gate 104 and the second conductive type drain region 112.Namely, it is positioned under the insulating spacers 108. The secondconductive type lightly doped region 114 a is, for example, formed inthe first conductive type substrate 100 between the gate 104 and thesecond conductive type drain region 112. Namely, it is positioned underthe insulating spacers 108.

According to the semiconductor device shown in FIG. 1C, inasmuch as asecond conductive type lightly doped region 114 a and the firstconductive type lightly doped region 116 are formed at the sides of thedrain and have an opposite conductive type, the substrate 100 betweenthe second conductive type drain region 112 and the gate stays at thefirst conductive type, thereby the limit of high-voltage stress of theMOS device can be raised, so that the semiconductor device of thepresent invention under a high voltage.

FIG. 1D is a schematic cross-sectional view showing yet anotherpreferred embodiment of the semiconductor device of the presentinvention. In FIG. 1D, the same reference numbers are used to refer tothe same parts in FIG. 1A. Here, only the differences are described.

Please refer to FIG. 1D. The gate dielectric layer 102 a between thegate 104 and the first conductive type substrate 100 is provided with adifferent thickness near the second conductive type drain region 112 andnear the second conductive type source region 110. For example, the gatedielectric layer 102 a is provided with a thickness d1 near the secondconductive type source region 110 and a thickness d2 near the secondconductive type drain 112. The thickness d2 is larger than thickness d1.

According to the semiconductor device shown in FIG. 1D, inasmuch as thegate dielectric layer 102 a is relatively thick near the secondconductive type drain region 112, high voltage durability is therebyachieved. Consequently, the gate dielectric layer is exempted from beingdamaged while a high voltage is applied to the drain region.

According to the semiconductor device shown in FIG. 1D, the lightlydoped region with the same conductive type as the source region formedbetween the source region and the gate and the lightly doped region witha different conductive type from the drain region formed between thedrain region and the gate are taken as an example to describe herein.Other alternatives are as shown in FIG. 1B and FIG. 1C. The lightlydoped region with an opposite conductive type to the drain region isformed between the drain region and the gate, or two lightly dopedregions having opposite conductive types are formed in the substratebetween the drain region and the gate so as to neutralize the substratebetween the drain region and the gate.

Inasmuch as the lightly doped region having a same conductive type asthe source region is formed between the source region and the gate, butno lightly doped region is formed between the drain region and the gate.Even forming a neutral substrate at the sides of the drain region orforming a lightly doped region with an opposite conductive type to thedrain region at the sides of the drain region are two other alternativesfor the semiconductor device of the present invention. Accordingly, ahigh breakdown voltage can be provided to raise the limit of thehigh-voltage stress of the MOS device and to operate the semiconductordevice of the present invention under a high voltage.

The method of fabricating the semiconductor device in the presentinvention is explained thereupon. FIGS. 2A through 2E are schematiccross-sectional views showing the steps for fabricating a semiconductordevice according to a preferred embodiment of the present invention.

Please refer to FIG. 2A. First, a first conductive type substrate 200 isprovided. A dielectric layer 202 and a conductive layer 204 are formedon the substrate 200 sequentially. The first conductive type substrate200 is a silicon substrate, for example. The material of the dielectriclayer 202 is, for example, silicon oxide. The dielectric layer isformed, for example, by thermal oxidation. The material of theconductive layer 204 is, for example, doped polysilicon. The method forforming conductive layer 204 includes forming a layer of undopedpolysilicon by chemical vapor deposition, and then performing anion-implantation process; or adopting an in-situ implanting operation ina chemical vapor deposition process.

Please refer to FIG. 2B. The conductive layer 204 and the dielectriclayer 202 are patterned to form the gate 204 a and the gate dielectriclayer 202 a. The patterned conductive layer 204 and the dielectric layer202 are formed, for example, by performing photolithographic and etchingprocesses. Then, a dielectric layer 206 is formed on the substrate 200.The material of the dielectric layer 206 is, for example, silicon oxide.The dielectric layer 206 is formed by thermal oxidation or chemicalvapor deposition, for example.

Please refer to FIG. 2C. A patterned photoresist layer 208 exposing thesubstrate 200 at one side of the gate 204 a is formed on the substrate200. The patterned photoresist layer 208 is formed by performing aphotolithographic process, for example. A dopant implantation process210 is performed by using the patterned photoresist layer 208 as a maskto form a second conductive type lightly doped region 212 in thesubstrate 200. The dopant implantation process 210 is, for example, toimplant dopants in the substrate 200 through an ion implantationprocess.

Please refer to FIG. 2D. After the patterned photoresist layer 208 isremoved, insulating spacers 214 are formed at the side walls of the gate204. The material of the insulating spacers 214 is silicon oxide,silicon nitride, or SiON, for example. The insulating spacers 214 are,for example, formed by performing a chemical vapor deposition process atfirst to form an insulating material layer, and removing a part of theinsulating material layer through an anisotropic etching operation.

Please refer to FIG. 2E. Subsequently, a dopant implantation process 216is performed by using the gate 204 a with insulating spacers 214 as amask to form a second conductive type source region 218 a and a secondconductive type drain region 218 b in the substrate 200. The dopantimplantation process 216 is, for example, to implant dopants in thesubstrate 200 through an ion implantation process.

FIGS. 3A through 3B are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to a preferredembodiment of the present invention. In FIGS. 3A and 3B, the samereference numbers are used to refer to the same parts in FIGS. 2Athrough 2E. Same descriptions are as well omitted.

Please refer to FIG. 3A. The steps depicted in FIG. 3A follow FIG. 2C.Namely, the patterned photoresist layer 208 is removed after the secondconductive type lightly doped region 212 is formed in the substrate 200.Afterward, another patterned photoresist layer 220 exposing thesubstrate 200 at another side (the side in opposition to the secondconductive type lightly doped region 212) of the gate 204 a is formed onthe substrate 200. The patterned photoresist layer 220 is formed byperforming a photolithographic process, for example. A dopantimplantation process 222 is performed by using the patterned photoresistlayer 220 as a mask to form a first conductive type lightly doped region224 in the substrate 200. The dopant implantation process 222 is, forexample, to implant dopants in the substrate 200 through an ionimplantation process.

Please refer to FIG. 3B. After the patterned photoresist layer 220 isremoved, insulating spacers 214 are formed at the side walls of the gate204. Subsequently, a dopant implantation process 216 is performed byusing the gate 204 a with the insulating spacers 214 as a mask to form asecond conductive type source region 218 a and a second conductive typedrain region 218 b in the substrate 200.

FIGS. 4A through 4C are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to anotherpreferred embodiment of the present invention. In FIGS. 4A through 4C,the same reference numbers are used to refer to the same parts in FIGS.2A through 2E. Same descriptions are as well omitted.

Please refer to FIG. 4A. The steps depicted in FIG. 4A follow FIG. 2B.Namely, after the gate 204 a, the gate dielectric layer 202 a, and thedielectric layer 206 are formed on the substrate 200. A dopantimplantation process 224 is performed by using the gate 204 a as a maskso as to form the second conductive type lightly doped regions 212 a and212 b on the substrate 200 at both sides of the gate 204 a. The dopantimplantation process 224 is, for example, to implant dopants in thesubstrate 200 through an ion implantation process.

Please refer to FIG. 4B. A patterned photoresist layer 226 exposing thesubstrate 200 at one side of the gate 204 a is formed on the substrate200. The patterned photoresist layer 226 is formed by performing aphotolithographic process, for example. Then, a dopant implantationprocess 228 is performed by using the patterned photoresist layer 226 asa mask to form a first conductive type lightly doped region 230 in thesubstrate 200. The dopant implantation process 228 is, for example, toimplant dopants in the substrate 200 through an ion implantationprocess.

Please refer to FIG. 4C. After the patterned photoresist layer 226 isremoved, insulating spacers 214 are formed at the side walls of the gate204. Subsequently, a dopant implantation process 216 is performed byusing the gate 204 a with the insulating spacers 214 as a mask to formthe second conductive type source region 218 a and the second conductivetype drain region 218 b in the substrate 200.

FIGS. 5A through 5D are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to a preferredembodiment of the present invention. In FIGS. 5A through 5E, the samereference numbers are used to refer to the same parts in FIGS. 2Athrough 2E. Same descriptions are as well omitted.

Please refer to FIG. 5A. First, the first conductive type substrate 200is provided. Then a dielectric layer 202 and a conductive layer 204 areformed on the substrate 200 sequentially. The first conductive typesubstrate 200 is a silicon substrate, for example. The dielectric layer202, for example, constitutes the dielectric layers 201 a and 201 b.Hence, the dielectric layer 202 has two types of thicknesses. Thematerial of the dielectric layer 202 is, for example, silicon oxide. Themethod of fabricating the dielectric layer 202 is, for example, to forma dielectric layer on the substrate 200 at first. Afterward, thedielectric layer is patterned to form the dielectric layer 201 a and thedielectric layer 201 b is then formed on the substrate 200. The materialof the conductive layer 204 is, for example, doped polysilicon. Themethod for forming the conductive layer 204 includes forming a layer ofundoped polysilicon by chemical vapor deposition and then performing aprocess of ion-implantation; or adopting an in-situ implanting operationin a chemical vapor deposition process.

Please refer to FIG. 5B. The conducting layer 204 and the dielectriclayer 202 are patterned to form the gate 204 a and the gate dielectriclayer 202 a. The patterned conductive layer 204 and the dielectric layer202 are formed, for example, by performing photolithographic and etchingprocesses. Then, the dielectric layer 206 is formed on the substrate200. The material of the dielectric layer 206 is, for example, siliconoxide. The dielectric layer 206 is formed by thermal oxidation orchemical vapor deposition, for instance.

Please refer to FIG. 5C. A patterned photoresist layer 208 exposing thesubstrate 200 at one side of the gate 204 a is formed on the substrate200. The patterned photoresist layer 208 is formed by performing aphotolithographic process, for example. A dopant implantation process210 is performed by using the patterned photoresist layer 208 as a maskto form a second conductive type lightly doped region 212 in thesubstrate 200. The second conductive type lightly doped region 212 isformed at the thinner side of the dielectric layer 202 a. The dopantimplantation process 210 is, for example, to implant dopants in thesubstrate 200 through an ion implantation process.

Please refer to FIG. 5D. After the patterned photoresist layer 208 isremoved, insulating spacers 214 are formed at the side walls of the gate204. Subsequently, a dopant implantation process 216 is performed byusing the gate 204 a with insulating spacers 214 as a mask to form thesecond conductive type source region 218 a and the second conductivetype drain region 218 b in the substrate 200. The dopant implantationprocess 216 is, for example, to implant dopants in the substrate 200through an ion implantation process. As stated in the method offabricating the semiconductor device shown in FIGS. 5A through 5D, thefabricating method disclosed in FIGS. 3A through 3B and FIGS. 4A through4C can be likewise applied to the method of fabricating the lightlydoped region.

According to the method of fabricating the semiconductor device shown inFIGS. 5A through 5D, the lightly doped region with the same conductivetype as the source region formed between the source region and the gateand the lightly doped region with a different conductive type from thedrain region formed between the drain region and the gate are taken asan example to describe herein. Other alternatives are as shown in FIGS.3A through 3B and FIGS. 4A through 4C. The lightly doped region with anopposite conductive type to the drain region is formed between the drainregion and the gate, or two lightly doped regions having oppositeconductive types are formed in the substrate between the drain regionand the gate so as to neutralize the substrate between the drain regionand the gate.

As stated above, the method of fabricating the semiconductor device ofthe present invention has a simple fabricating process which can beintegrated with the process of fabricating a conventional ComplementaryMetal Oxide Semiconductor (CMOS) so as to reduce the time of fabricatingthe device.

In conclusion, inasmuch as a lightly doped region having a sameconductive type as the source region is formed between the source regionand the gate, but on lightly doped region is formed between the drainregion and the gate. Even forming a neutral substrate at the sides ofthe drain region or forming a lightly doped region with an oppositeconductive type to the drain region at the sides of the drain region aretwo other alternatives for the semiconductor device of the presentinvention. If the semiconductor device is operated under a smallerturned-on current, a better device performance can be then achieved andthe limit of high-voltage stress can be raised so as to operate thesemiconductor device of the present invention under a high voltage.

Furthermore, since the method of fabricating the semiconductor device ofthe present invention can be integrated with the process of fabricatinga conventional Bipolar Complementary Metal Oxide Semiconductor (CMOS),the time of fabricating the device can be reduced without performing thephotolithographic and etching processes.

The above description provides a full and complete description of thepreferred embodiments of the present invention. Various modifications,alternate construction, and equivalent may be made by those skilled inthe art without changing the scope or spirit of the invention.Accordingly, the above description and illustrations should not beconstrued as limiting the scope of the invention which is defined by thefollowing claims.

What is claimed is:
 1. A method of fabricating a semiconductor device,comprising: providing a first conductive type substrate; forming a gateon the first conductive type substrate; forming a second conductive typefirst lightly doped region in the substrate at a first side of the gate;and forming a second conductive type source region in the substrate atthe first side of the gate, and forming a second conductive type drainregion at a second side of the gate, wherein the second conductive typefirst lightly doped region is formed in the first conductive typesubstrate between the second conductive type source region and the gate.2. The method of fabricating the semiconductor device of claim 1,wherein the first conductive type is a P-type while the secondconductive type is an N-type; or the first conductive type is an N-typewhile the second conductive type is a P-type.
 3. The method offabricating the semiconductor device of claim 1, further comprisingforming a first dielectric layer on the first conductive type substratebefore the step of forming the gate on the first conductive typesubstrate.
 4. The method of fabricating the semiconductor device ofclaim 3, wherein the first dielectric layer has a first thickness at thefirst side and a second thickness at the second side, and the secondthickness is larger than the first thickness.
 5. The method offabricating the semiconductor device of claim 1, wherein the steps offorming the second conductive type first lightly doped region in thefirst conductive type substrate at the first side of the gate comprise:forming a patterned photoresist layer exposing the first conductive typesubstrate at the first side of the gate on the substrate; performing anion implantation process to form the second conductive type firstlightly doped region; and removing the patterned photoresist layer. 6.The method of fabricating the semiconductor device of claim 1, furthercomprising forming a first conductive type lightly doped region in thesubstrate at the second side of the gate, wherein the first conductivetype lightly doped region is formed between the second conductive typedrain region and the gate.
 7. The method of fabricating thesemiconductor device of claim 6, wherein the steps of forming the secondconductive type first lightly doped region in the first conductive typesubstrate at the first side of the gate and forming the first conductivetype lightly doped region in the substrate at the second side of thegate comprise: forming a first patterned photoresist layer exposing thefirst conductive type substrate at the first side of the gate on thesubstrate; performing a first ion implantation process to form thesecond conductive type first lightly doped region; removing the firstpatterned photoresist layer; forming a second patterned photoresistlayer exposing the first conductive type substrate at the second side ofthe gate on the substrate; performing a second ion implantation processto form the first conductive type lightly doped region; and removing thesecond patterned photoresist layer.
 8. The method of fabricating thesemiconductor device of claim 6, further comprising: forming a secondconductive type second lightly doped region in the substrate at thesecond side of the gate, wherein the second conductive type secondlightly doped region is formed between the second conductive type drainregion and the gate.
 9. The method of fabricating the semiconductordevice of claim 8, wherein the steps of forming the second conductivetype first lightly doped region and the second conductive type secondlightly doped region in the first conductive type substrate at the firstside and the second side of the gate and forming the first conductivetype lightly doped region in the substrate at the second side of thegate comprise: performing a first ion implantation process to form thesecond conductive type first lightly doped region and the secondconductive type second lightly doped region; forming a patternedphotoresist layer exposing the first conductive type substrate at thesecond side of the gate on the substrate; performing a second ionimplantation process to form the first conductive type lightly dopedregion; and removing the patterned photoresist layer.
 10. The method offabricating the semiconductor device of claim 1, further comprisingforming insulating spacers at the side walls of the gate.